As memory chip density increases, the defect density resulting from the integrated circuit fabrication process limits the functional yield. While an increasing amount of attention has been focused on controlling the fabrication process to limit defect density, as chip geometries shrink and chip size increases, it becomes increasingly difficult to control the process tightly enough to achieve high natural functional yield.
A number of techniques, such as redundancy schemes, have been utilized to increase the functional yield of memory devices. Basically, a redundancy scheme provides extra rows and/or columns in the memory array which can be used to replace defective bits, defective rows, or defective columns.
FIG. 1 shows a block diagram of a memory chip 10 with row and column redundancy. The memory array of chip 10 is subdivided into 4 quadrants (Q1-Q4) by the X row and Y column decoders. This "quadrant" type of architecture is utilized to provide increased access speed to memory cells within the array. A memory cell in memory array quadrant Q2 is accessed by simultaneously applying an X-address to row decoders 12 and a Y-address to column decoders 14 whereby a single row and a single column are selected in quadrant Q2. The cross point of the selected row and the selected column identifies the memory cell that is accessed. The data stored in that cell is then transferred onto the I/O lines where it is amplified and transferred onto an I/O bus 16.
To write into the accessed cell, X-row and Y-column addresses are applied to the row and column decoders, which in turn select a single cell to which the data to be written is transferred from I/O bus 16.
During the manufacturing of a monolithic memory device, process defects can disable a row or a column or a single bit or multiple bits, making the chip unusable. To overcome these defects, an extra row 18 and an extra column 20 are added to each of the four quadrants Ql-Q4. If there is a defect in a given quadrant, making a normal row 22 or a normal column 24 or a single bit fail, then that particular row or column or bit is disabled permanently and is replaced by the redundant row 18 or column 20 for that quadrant. Of course, those skilled in the art will appreciate that multiple redundant rows and columns can be included in each quadrant as chip size and cost permit.
The above-described redundancy approach to handling chip defects has limitations in that a redundant row can only replace a defective row or a single bit and a redundant column can only replace a defective column or a single bit. This replacement scheme rigidity, in combination with array segmentation, limits the effectiveness of the redundancy scheme and inhibits its application to waferscale integration.